W-CSP uses interconnection technology to effectively utilize the chip area by making it possible to form electrodes over the entire chip surface. This eliminates the need for the wire bonding space required by previous wiring methods. Also, electrodes are formed using copper posts for a simple structure.

Interconnection and Copper Posts (Before Resin Encapsulation)

Finished Package

All of this means that the area of the finished package is exactly the same compact size as the original chip. It also simplifies mounting and contributes to easier high-density mounting. W-CSP is the perfect choice for packaging chips used in portable telephones, digital cameras, and other applications where mounting space is severely restricted.

CASIO MICRONICS simulation technology allows us to provide our customers with the following W-CSP simulations. Thermal Stress Analysis Thermal Resistance Analysis Other Solutions (Thin Configuration, High Reliability, Low Heat/Low Resistance)

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